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DFT Technical Manager/Lead
USA-CA-San Jose - tanrg.com
Lead test methodology development and implementation of test chips in advanced process nodes
Perform top/block-level DFT insertion including scan compression, boundary scan, 1500 wrapper, ATPG and pattern simulation
Verify DFT circuitry and interface with other blocks, debug timing
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Seen at tanrg.com 2536 days ago
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